DELiRium, for Deep Learning compiler on reconfigurable hardware, is a tool that aims at deploying AI models on FPGA devices. DELiRium basically inputs a pretrained neural network (that takes the shape of a standard ONNX model) and outputs a hardware description that can be implanted on FPGAs or ASICs.

The tool is engineered to deliver both low power and real time performance through two main features. The first one relies on the dataflow processing to exploit all the parallelism exhibited by neural nets. The second one leverages on the fine granularity of FPGAs and ASICs to reduce the footprint –and thus the energy consumption– of the generated circuits.

Using Delirum in 5 steps

1. Run the windows installer or unzip the linux executable.

2. Open a cmd or linux terminal in the directory containing the delirium executable. Note that you should also have the lib_hdl_free folder in this current directory.

3. Run the tool ./delirium with the desired arguments:

• --onnx specifies the path to the pre-trained ONNX model.
• --out sets the output generated VHDL directory (hdl_generated by default).
• --nbits specifies the bitwidth of data and weights (8 bits by default).
• --stop selects the layer where delirium stops its parsing (Stops at the first fully connected layer by default).
• --copy forces the tool to create a copy of the VHDL library in the working directory

For instance, the following example generates the VHDL code implementing the first layers of a pre-trained cifar10 classifier.

./delirium --onnx ../example/cifar10/cifar10.onnx --stop CONV3 --copy
================================================= 
    DELiRium VHDL Genrator:
    ONNX model: ../example/cifar10/cifar10.onnx
    VHDL top level: hdl_generated/cifar10_main.vhd
    VHDL parameters: hdl_generated/params.vhd
    Data and weights precision: 8 bits
    Implementing all layers until: CONV3
=================================================  

Notice how the tool generates 3 files:

• params.vhd contains the CNN hyper-parameters (kernel sizes, number of feature maps, input resolution etc.) and parameters (i.e weights) which are hard-coded as VHDL constants.
• bitwidths.vhd defines the bitwidths of feature maps, pixels and accumulators.
• XXXX_main.vhd is the top level entity describing the CNN structure.

5. You can now create a project using your favorite synthesis/simulation tool.

• In Quartus or Vivado, create a new project.
• Set the top level entity to XXXX_main.
• Add the generated VHDL designs (i.e those in the hdl_generated directory).
• Add the provided library files (i.e the files in hdl_lib).
• Set your compiler settings to VHDL 2008

Next, follow your usual FPGA conception flow (synthesize, place and root, …) and enjoy!!!

For an evaluation version of DELiRium, please contact us.