Training course: Embedded Hardware design

Course Objectives

Embedded Hardware design ” is four-day hands-on course that provide fundamental concepts and techniques for FPGA-based hardware design principles:

  • Make a difference between imperative language and HDL
  • Use concurrent and sequential control structure to regulate information flow
  • Implement common VHDL constructs (Finite State Machines [FSMs], data structures)
  • Identify and implement coding best practices

Who Should Attend?

Researchers, Lecturers, Scientists and Engineers who want to use VHDL or Verilog effectively for modeling, design, and synthesis of digital designs.

Course outline

  • Build VHDL models using language constructs such as assignment statements, process statements, if statements, case statements and loops
  • Use VHDL design units including entities, architectures,
  • Understand the simulation versus synthesis environment
  • Create synthesizable models (behavioral coding style)
  • Use VHDL component instantiations to create hierarchy (structural coding style)


This course request the following prior knowledge:

  • Background in digital logic design
  • Prior knowledge of a programming language is a plus


This training course can be taught in English, French, Italian and Arabic.